CyberRota Analysis
AI-GeneratedThe vulnerability arises from an output mismatch between the RTL and the netlist of the openRISC OR1200 CPU output port, potentially causing unexpected behavior in systems utilizing this architecture. This critical flaw could lead to severe operational disruptions or security breaches, making it imperative for developers and organizations using openRISC OR1200-based systems to prioritize remediation efforts.
Public Exploit Signal
A public exploit, PoC, GitHub repository or Metasploit reference was detected for this CVE.
Note: these links are listed for security research and verification purposes only.
Original NVD Description
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior.